1. Field of the Invention
The present invention relates to a non-volatile semiconductor storage system, and particularly, to a nonvolatile semiconductor storage device enabled to store multiple bits in one memory cell.
2. Description of the Related Art
One of the well-known non-volatile semiconductor storage systems is a NAND cell type flash memory. The NAND cell type flash memory includes a memory cell array including a plurality of NAND cell units. Each NAND cell unit includes a plurality of memory cells connected in series and two selection transistors connected to both ends thereof.
The memory cell holds, in an erase state, data “1” and has a negative threshold voltage. In a data write operation, a floating gate of the memory cell is injected with electrons to write data “0”, and the memory cell has a positive threshold voltage. The NAND cell type flash memory may change the threshold voltage of the memory cell only from a lower value to a higher value in a data write operation, and may change the threshold voltage in the reverse direction (from a higher value to a lower value) only by an erase operation per block.
To increase memory capacity, current developments are directed to a so-called multi-value NAND cell type flash memory that stores two or more bits of information in one memory cell. For example, when 3 bits are stored in one memory cell, one memory cell involves 23=8 different threshold voltage distributions (see, for example, Japanese Patent Laid-Open No. 2008-077810).
Meanwhile, since the NAND cell type flash memory is usually controlled in a unit of power-of-two bits of data, host devices utilizing such the NAND cell type flash memory are also designed for data control in a unit of power-of-two bits of data.
However, in the NAND cell type flash memory where 3 bits are stored in one memory cell, for example, the amount of data that is subject to data-erase at a time in a data erase unit (block) is not a power-of-two bits of data. As such, there may be a mismatch (discrepancy) between the logic block size of a host device and the data erase unit of the NAND cell type flash memory. Consequently, such situations frequently arise where data copy operations are required within the system, causing additional overhead in the system. This may result in serious disruption to normal operation in some applications, such as video recording that requires data write/read to be performed in a continuous manner. This issue may arise not only when performing multi-value storage of 3 bits per cell, but also when performing that of N bits per cell (where N is a natural number more than 3, other than a power of two).